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Effects of EMI on Digital Systems Participants: Prof. P. Mazumder The University of Michigan Prof. M. Bridgwood Clemson University Prof. S. Dutt University of Illinois, Chicago Conducted WB and NB Interaction with Digital Devices Impedances of Interfaces through Switching - Inputs, Outputs, Control Lines, Power supplies Vulnerability Thresholds - Disruption and Damage - Single Nodes - Multiple Nodes and Devices Waveforms - Pulses - Damped Rings DRAM Input Circuit Structure Modeling of Simple Capacitive StructureThrough Breakdown Events SIA Roadmap - IC Technology Task 3.2.1: EMI generation due to Tr. Switching Task 3.2.2: Effects of EMI on chip operations Task 3.2.3: EMI Simulator Design Noise Distribution Paths Direct radiation from chip surface Caused by high-frequency current within the chip Level of radiation is small in comparison to the following ones Conducting noise from the signal ports Off-chip wires act as antennae Effect of this noise source is significant … but it’s an easy problem Power-line conducting noise High-frequency large power/ground current Most significant source of EMI problem … and is difficult to solve Power-Line Conducting Noise Modeling core power network Power-line capacitance modeling Switching current model Power Network Modeling Switching Current Simulation Time-varying switching current consumed in circuit blocks is first simulated assuming ideal power supply voltage using SPICE Circuit simulation is performed for the power network with the switching current information added By iterating this annotation process, one can achieve better simulation accuracy Power-Line Conducting Noise Clock Network Transmission line modeling of clock wires Differential Quadrature Method (DQM) Model Reduction by Krylov Subspace Method Study of clock jitters and synchronization fa