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AD转换器 MUSICLIBRARY IEEE; --8位二进制全加器顶层设计描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder8a IS PORT (a0,b0,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,cin : IN STD_LOGIC; cout,sum0,sum1,sum2,sum3,sum4,sum5,sum6,sum7 : OUT STD_LOGIC ); END ENTITY f_adder8a; ARCHITECTURE fd1 OF f_adder8a IS COMPONENT f_adder PORT ( ain,bin,cin : IN STD_LOGIC; cout,sum : OUT STD_LOGIC); END COMPONENT; SIGNAL d,e,f,g,h,i,j: STD_LOGIC; BEGIN u1 : f_adder PORT MAP(ain=a0,bin=b0,cin=cin,sum=sum0,cout=d); u2 : f_adder PORT MAP(ain=a1,bin=b1,cin=d,sum=sum1,cout=e); u3 : f_adder PORT MAP(ain=a2,bin=b2,cin=e,sum=sum2,cout=f); u4 : f_adder PORT MAP(ain=a3,bin=b3,cin=f,sum=sum3,cout=g); u5 : f_adder PORT MAP(ain=a4,bin=b4,cin=g,sum=sum4,cout=h); u6 : f_adder PORT MAP(ain=a5,bin=b5,cin=h,sum=sum5,cout=i); u7 : f_adder PORT MAP(ain=a6,bin=b6,cin=i,sum=sum6,cout=j); u8 : f_adder PORT MAP(ain=a7,bin=b7,cin=j,sum=sum7,cout=cout); END ARCHITECTURE fd1; 八位全加器 八位数码显示电路乘法器七段数码管译码电路数字时钟LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT (CLK,RST,EN : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT10; ARCHITECTURE behav OF CNT10 IS BEGIN PROCESS(CLK, RST, EN) VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF RST = 1 THEN CQI := (OTHERS =0) ; --计数器复位 ELSIF CLKEVENT AND CLK=1 THEN --检测时钟上升沿 IF EN = 1 THEN --检测是否允许计数 IF CQI 1001 THEN CQI := CQI + 1; --允许计数 ELSE CQI := (OTHERS =0);--大于9，计数值清零 END IF; END IF; END IF; IF CQI = 1001 THEN COUT = 1; --计数大于9，输出进位信号 ELSE COUT = 0; END IF; CQ = CQI; --将计数值向端口输出 END PROCESS; END behav;四位计数器四位频率计LIBRARY IEEE; --测频控制器 USE IEEE.STD_LO