CPLD实验 数字时钟 波形发生器 简单组合逻辑设计.pptVIP

* CPLD实验 一实验要求： 熟练运用MAX+PLUSII分析组合逻辑电路、时序电路，能够运用VHDL对简单的逻辑电路功能进行描述。 二、实验结果 要求对仿真结果生成的仿真波形文件进行保存，并对结果进行分析说明。 实验1：简单组合逻辑设计 实验2：数码管扫描电路 library IEEE; use IEEE.std_logic_1164.all; entity xdeled is port ( d_in: in STD_LOGIC_VECTOR (3 downto 0); a: out STD_LOGIC; b: out STD_LOGIC; c: out STD_LOGIC; d: out STD_LOGIC; e: out STD_LOGIC; f: out STD_LOGIC; g: out STD_LOGIC ); end xdeled; begin -- enter your statements here process(d_in) type data_out is array(0 to 6) of std_logic; variable outp: data_out; begin case d_in is when 0000 = outp := 1111110; when 0001 = outp := 0110000; when 0010 = outp := 1101101; when 0011 = outp := 1111001; when 0100 = outp := 0110011; when 0101 = outp := 1011011; when 0110 = outp := 1011111; when 0111 = outp := 1110000; when 1000 = outp := 1111111; when 1001 = outp := 1111011; when 1010 = outp := 1110111; when 1011 = outp := 0011111; when 1100 = outp := 1001110; when 1101 = outp := 0111101; when 1110 = outp := 1001111; when 1111 = outp := 1000111; when others = null; end case; a = outp(0); b = outp(1); c = outp(2); d = outp(3); e = outp(4); f = outp(5); g = outp(6); end process; end xdeled; 实验3：计数器电路设计（8位二进制同步计数器） 实验4：波形发生器 1、正斜率斜波 2、负斜率斜波 3、锯齿波 4、递增阶梯波 library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ? entity wavegenerator is port ( clk: in STD_LOGIC; reset: in STD_LOGIC; mode: in STD_LOGIC_VECTOR (1 downto 0); d_out: out STD_LOGIC_VECTOR (7 downto 0) ); end wavegenerator; architecture wavegenerator_arch of wavegenerator is signal da : std_logic_vector(7 downto 0); begin -- enter your statements here process(clk,reset,mode,da) variable porn : std_logic; begin if reset=0 then da d_out porn:=0; else if clk=1 and clkevent then case mode is