FPGA-ARM通信代码.docVIP

library?ieee; use?ieee.std_logic_1164.all; use?ieee.std_logic_arith.all; use?ieee.std_logic_unsigned.all; ----FPGA内部寄存器地址定义： package??interface?is constant?addr_reg1?:?std_logic_vector(9?downto?0)?:=?0000000000; constant?addr_reg2?:?std_logic_vector(9?downto?0)?:=?0000000001; constant?addr_reg3?:?std_logic_vector(9?downto?0)?:=?0000000010; constant?addr_reg4?:?std_logic_vector(9?downto?0)?:=?0000000011; end; library?ieee; use?ieee.std_logic_1164.all; use?ieee.std_logic_arith.all; use?ieee.std_logic_unsigned.all; use?work.interface.all; entity?arm_fpga?is port( mcudata?:?in