数字电路与逻辑设计-VHDL-计数器8421-分频器.docVIP

计数器8421 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jishuqi8421 is port(clear,clk: in std_logic; q: out std_logic_vector(3 downto 0)); end entity; architecture a of jishuqi8421 is signal tmp:std_logic_vector(3 downto 0); begin process (clk) begin if (clkevent and clk=1)then if clear=0 then tmp=0000; elsif tmp=1001 then tmp=0000; else tmp=tmp+1; end if ; end if ; end process; q=tmp; end a; 波形图 总时间性10US，5000NS，250NS 分频器8 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div_8 is port(clear,clk: in std_logic; clk_out: out std_logic); end entity; architecture a of div_8 is signal tmp:integer range 0 to 7; begin process (clk,clear) begin if clear=0 then tmp=0; elsif clkevent and clk=1 then if tmp=7 then tmp=0; else tmp=tmp+1; end if ; if tmp4 then clk_out=1; else clk_out=0; end if ; end if ; end process; end a; 波形图 总时间性10US，5000NS，300NS 3 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity light is port(reset,swf,clk: in std_logic; cout: out std_logic_vector(7 downto 0)); end entity; architecture a of light is signal s1:std_logic_vector(3 downto 0); signal s2:std_logic_vector(3 downto 0); begin one:process (clk,reset) begin if(reset=1) then s1=1111;s2=1111; elsif (clkevent and clk=1)then if(s1=1101) then s1=s1+1; else s1=0000; end if; if(s2=0110)then s2=s2+1; else s2=0000; end if ; end if; end process one; two:process (clk,s1,s2,swf) begin if(swf=0)then case s1 is when0000=cout when0001=cout when0010=cout when0011=cout when0100=cout when0101=cout when0110=cout when0111=cout when1000=cout when1001=cout when1010=cout when1011=cout when1100=cout when1101=cout when1110=cout when others=cout end case; else case s2 is when0000=cout when