VHDL作业及解答.docVIP

VHDL作业 读例6.3、6.7、6.9代码。 什么是桶形移位寄存器? 桶形移位器用来有效地实现移位、循环移位和位操作，被广泛地用于乘法及其他操作中。它可以在一个时钟周期内实现64位同时移位，也可对任何一种数据类型移任意位数。桶形移位器与ALU并行操作，可加速乘法、除法、位操作，移位和循环移位操作。entity Buffer IS port(enable,datain: in std_logic; dataout: out std_logic); end Buffer; atchitecture Buffer1 of Buffer IS begin process(datain,enable) begin if (enable= ‘1’) then dataout = datain; else dataout = ‘Z’; end if; end process; end Buffer1; 总线缓冲器 entity oeseqbus is port(enable: in std_logic; datain: in std_logic_vector(7 downto 0); dataout: out std_logic_vector(7 downto 0)); end oeseqbus; atchitecture sequential of oeseqbus is begin process(datain,enable) begin if (enable= ‘1’) then dataout = datain; else dataout = (others = ‘Z’); end if; end process; end sequential; 锁存器实例： library ieee; use ieee.std_logic_1164.all; entity latch is port(datain: in std_lagic; enable: in std_logic; dataout: out std_logic); end latch; atchitecture behav of latch is begin process(datain,enable) begin if(enable = ‘1’) then dataout = datain; end if; end process; end behav; 寄存器：寄存器一般由多位触发器连接而成，通常有锁存寄存器和移位寄存器等。 锁存寄存器示例： entity oeseqbus is port(clk: in std_logic; datain: in std_logic_vector(7 downto 0); dataout: out std_logic_vector(7 downto 0)); end oeseqbus; atchitecture sequential of oeseqbus is begin process(clk) begin if (clk’event and clk’last_value=’0’) then dataout = datain; end if; end process; end sequential; 串入串出(SISO)移位寄存器示例： library ieee; use ieee.std_logic_1164.all; entity siso is port(datain : in std_logic; clk : in std_logic; dataout : out std_logic); endi siso; architecture behav of siso is signal q: stc_logic_vector(3 downto 0); begin process(vlk0 begin if (clk’event and clk=’1’) then q(0) = datain; for i in 1 to 3 loop q(