SN74LVC32373AZKER,SN74LVC32373AGKER,SN74LVC32373AGKER,SN74LVC32373AGKER, 规格书,Datasheet 资料12.pdf

SN74LVC32373A 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES575 – JUNE 2004 – REVISED AUGUST 2005 FEATURES • Member of the Texas Instruments Widebus+™ • Ioff Supports Partial-Power-Down Mode Family Operation • Operates From 1.65 V to 3.6 V • Supports Mixed-Mode Signal Operation (5-V • Inputs Accept Voltages to 5.5 V Input and Output Voltages With 3.3-V VCC) • Max t of 4.2 ns at 3.3 V • Latch-Up Performance Exceeds 100 mA Per pd JESD 78, Class II • Typical VOLP (Output Ground Bounce) 0.8 V at V = 3.3 V, T = 25°C • ESD Protection Exceeds JESD 22 CC A • Typical VOHV (Output VOH Undershoot) 2 V at – 2000-V Human-Body Model (A114-A) VCC = 3.3 V, TA = 25°C – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high