ASIPS美国名校嵌入式课程.pptVIP

Topics CPU selection. Application-specific processors in SoCs. Instruction set design. Compilers. Figures of merit in CPU selection Performance on the application: Average case. Worst-case. Power/energy consumption. Interrupt handling latency. Context switch time. Other issues in CPU selection Code compatibility. Development environment. Fab support. CPU families example: ARM Low end: No cache. No floating point. No MMU. High end: Cache. Floating-point. MMU. CPU vs. DSP First DSP (ATT DSP16) had: Multiplier; Harvard architecture. Now DSP is a marketing term. ARM is a DSP. Configurable vs. reconfigurable Configurable: CPU architectural features are selected at design time. Reconfigurable: Hardware can be reconfigured in the field. May be dynamically reconfigured during execution. Tensilica configurable processors Configurability: Processor parameters (cache size, etc.) Instructions. Result: HDL model for processor. Software development environment. Xtensa configurability Instruction set: ALU extensions, coprocessors, wide instructions, DSP-style, function unit implementation. Memory: I cache config, D cache config, memory protection/translation, address space size, mapping of special-purpose memories, DMA access. Interface: Bus width, protocol, system register access, JTAG, queue interfaces to other processors. Peripherals: Timers, interrupts, exceptions, remote debug. TIE extensions TIE language used to define instruction set defintions. State declarations. Instruction encodings and formats. Operation descriptions. TIE example (Rowen) Regfile LR 16 128 l Operation add128 {out LR sr, in LR ss, in LR st} { assign sr = st + ss;} Using instructions in C main() { int i; LR src1[256], src2[256], src3[256]; for (i=0; i256; i++) dest[i] = add128(src1[i],src2[i]); Performance improvement Compare Xtensa optimized vs. Xtensa out-of-the-box: Compare performance/MHz. EEMBC ConsumerMark: Xtensa optimized: 2.02. Xtensa out-of-the-box: 0.66. EEMBC TeleMark: X