基于FPGA的人脸识别项目.pptVIP

Facial Expression Recognition Based on field Programmable Gate Array Jzau-Sheng Lin, Shao-Han Liou, Wu-Chih Hsieh, Yu-Yi Liao, HongChao Wang*, and QingHua Lan* Department of Computer Science and Information Engineering National Chin-Yi University of Technology *Embedded Laboratory, Huaxia Vocation College, Xiamen, China Outline 1. Introduction 2. DWT-CMAC (1/3) 2. DWT-CMAC (2/3) The proposed CMAC The weight can be adjusted with the steeping descent rule as follows: 2. DWT-CMAC (3/3) 3. Preprocessing for FFE (1/2) 3. Preprocessing for FFE (2/2) 4. Hardware Implementation 4.1 DWT IP (1/2) 4.1 DWT IP (2/2) 4.2 CMAC IP (1/4) The training phase The input data low-frequency band (32×32 bytes) of Haar DWT transformation ? divide a nun-overlap 2×2 block as a training sample ( to simplify the input coding circuit of the CMAC ) SRAM To store the coding addresses with a size of 16×16×12=3072 bits. 4.2 CMAC IP (2/4) 4.2 CMAC IP (3/4) The recognition phase The unknown input data ? memory The Weight Summation Module to find the weights To sum them as total weights to express the intensities for different facial expressions. To use the Max module to find the maximum facial-expression intensity. 4.2 CMAC IP (4/4) 5. Experimental results (1/3) The facial express patterns JAFFE database 120 subjects for training 60 subjects for testing The image interface FPGA SoC platform with Virtex IV-ML40X The parameter of CMAC network The learning rate was set 0.05 The sizes of cluster were set 2, 4, and 6 bits 5. Experimental results (2/3) 5. Experimental results (3/3) 6. Conclusion The proposed 2D DWT IP transform difference images from spatial domain to frequency domain to yield 1024 lower-frequency coefficients in LL-band data as the input signals that were quantized as a binary manner and fed into the CMAC IP. The CMAC IP used a proper size of 4-bit cluster and a learning rate 0.05 has successfully obtained a better recognition rate about 88.3%. * 5. Experimental results 4. H