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CMOS版图XOR
实验目的
⑴首先在S-EDIT中画出异或门的原理图
⑵根据原理图,在L-EDIT中画出异或门的版图
⑶由版图提取与非门的.spc文件
⑷在T-SPICE中进行仿真
实验步骤
⑴在S-EDIT中画出异或门的原理图
⑵根据原理图,在L-EDIT中画出异或门的版图
⑶由版图提取与非门的.spc文件
* Circuit Extracted by Tanner Researchs L-Edit Version 9.00 / Extract Version 9.00 ;
* TDB File: D:\zlg\Tanner\LEdit90\Samples\SPR\example1\Layout1.tdb
* Cell: Cell0 Version 1.19
* Extract Definition File: lights.ext
* Extract Date and Time: 06/04/2011 - 15:04
.tran/op 2n 80n method=bdf
.include D:\zlg\Tanner\TSpice70\models\ml2_125.md
.print tran v(A) v(B) v(F)
v1 Vdd Gnd 5
v2 A Gnd PULSE (0 5 0 0 0 8n 20n)
v3 B Gnd PULSE (0 5 10n 0 0 8n 20n)
.include D:\zlg\Tanner\LEdit90\Samples\SPR\example1\ext_devc.md
* Warning: Layers with Unassigned AREA Capacitance.
* Poly Resistor ID
* Poly2 Resistor ID
* N Diff Resistor ID
* P Diff Resistor ID
* P Base Resistor ID
* N Well Resistor ID
* Warning: Layers with Unassigned FRINGE Capacitance.
* Poly1-Poly2 Capacitor ID
* Poly Resistor ID
* Poly2 Resistor ID
* N Diff Resistor ID
* P Diff Resistor ID
* P Base Resistor ID
* N Well Resistor ID
* Pad Comment
* Warning: Layers with Zero Resistance.
* Poly1-Poly2 Capacitor ID
* NMOS Capacitor ID
* PMOS Capacitor ID
* Pad Comment
* NODE NAME ALIASES
* 2 = F (66,20)
* 3 = B (37,19)
* 4 = A (-24.5,18.5)
* 6 = Gnd (156,-12)
* 8 = Vdd (165,54.5)
M1 Vdd B 7 Vdd PMOS L=2u W=6u
* M1 DRAIN GATE SOURCE BULK (135 36 137 42)
M2 7 A Vdd Vdd PMOS L=2u W=6u
* M2 DRAIN GATE SOURCE BULK (85 36 87 42)
M3 Gnd B 1 Gnd NMOS L=2u W=6u
* M3 DRAIN GATE SOURCE BULK (135 -8 137 -2)
M4 1 A F Gnd NMOS L=2u W=6u
* M4 DRAIN GATE SOURCE BULK (85 -8 87 -2)
M5 5 B 9 Vdd PMOS L=2u W=6u
* M5 DRAIN GATE SOURCE BULK (20 36 22 42)
M6 9 A Vdd Vdd PMOS L=2u W=6u
* M6 DRAIN GATE SOURCE BULK (-5 36 -3 42)
M7 F 5 7 Vdd PMOS L=2u W=6u
* M7 DRAIN GATE SOURCE BULK (48 36 50 42)
M8 Gnd B 5 Gnd NMOS L=2u W=6u
* M8 DRAIN GATE SOURCE BULK (20 -8 22 -2)
M9 5 A Gnd Gnd NMOS L=2u W=6u
* M9 DRAIN GAT
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