基于xilinx fpgasae as5643仿真设备设计与实现-design and implementation of sae as 5643 simulation device based on xilinx fpga.docxVIP

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基于xilinx fpgasae as5643仿真设备设计与实现-design and implementation of sae as 5643 simulation device based on xilinx fpga.docx

基于xilinx fpgasae as5643仿真设备设计与实现-design and implementation of sae as 5643 simulation device based on xilinx fpga

摘 要航空系统的飞速发展,对数据传输带宽、确定性、实时性等性能要求也越来 越高,为了满足新一代航空系统的需求和发展,必须对标准的 IEEE-1394B 总线 协议加以限定,形成了新的 1394B 接口需求——SAE AS5643。为了仿真航空系 统中 1394 总线系统的可靠性,需要设计一系列地面虚拟仿真设备,其中包含了 CC 仿真卡。CC 仿真卡是用于在地面上模拟 1394 总线根节点功能的虚拟仿真设备,包含 3 个 CC 节点。系统中,CC 仿真卡利用根节点功能连入系统总线,完成 AS5643 通信协议处理以及提供外设和主机系统的信息交互。论文中阐述了基于 FPGA 的 CC 仿真卡设计实现,所有模块用 Verilog 代码实现,并结合 Xilinx ISE 开发环境和 QustaSim 仿真工具对 CC 仿真卡进行了时序仿真,并通过 FPGA 验证了正确性, 完成了 FPGA 的设计与实现。论文中所阐述的设计均已实现,FPGA 综合报告已经满足,虚拟仿真与 FPGA 测试已经开展,基本功能已经达到设计目的。该设计实现了单个板卡 3 个 CC 节 点多通道同步,具有数据收发、故障注入、电源管理、心跳字初始值自设定、VPC 与 CRC 自检测等功能。关键词:FPGA机载总线控制计算机仿真卡AbstractWith the rapid development of aviation system, the bandwidth, accuracy and instantaneity of data transmission are increasingly significant. To address the requirement of new generation aviation system, standard IEEE-1394B bus protocol should be restricted. Thus new 1394B interface requirement—SAE AS5643 was developed. To simulate the reliability of 1394 bus system in aviation system, a series of ground virtual simulation devices including CC simulation_card were designed.CC card is a visual simulator to simulate the node function of 1394 buses on the ground. It contains three nodes ,In the system CC simulation_card can be linked to system bus through the root node function, thus achieving AS5643 communication protocol processing and information interaction between peripheral and host system.This thesis detailed the design of CC simulation_card based on FPGA. All modules were achieved by Verilog coding. To test the accuracy of FPGA, the timing simulation of CC simulation card was performed through Xilinx ISE development environment and QustaSim simulator. The design of FPGA was achieved.Designs have been achieved as set out in the thesis, FPGA synthesis report had been met, virtual simulation and FPGA test has been carried out, the basic features already meet the design objectives.It contains three nodes with the function of data sending or receiving, faults injection, buttery management, self-setting of heart be

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