Intel 的Multiple Instruction Stream Processor(MISP).pptVIP

Multiple Instruction Stream Processor (MISP) R. Hankins, G. Chinya, J. Collins, P. Wang, R. Rakvic, H. Wang and J. Shen, in Proceedings of the 33rd International Symposium on Computer Architecture June 2006. Agenda Motivation / Introduction Paper Contributions MISP Architecture Prototype System / Experimental Results Final thoughts / Conclusions Future of Multi-Core “We (Intel) plan to deliver Intel processors over the next decade that will have dozens, and even hundreds of cores in some cases.” [1] “…breaking up functions into many concurrent operations and distributing these across many s