宽锁定范围时钟数据恢复电路的分析与设计-analysis and design of clock data recovery circuit with wide locking range.docxVIP

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宽锁定范围时钟数据恢复电路的分析与设计-analysis and design of clock data recovery circuit with wide locking range.docx

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宽锁定范围时钟数据恢复电路的分析与设计-analysis and design of clock data recovery circuit with wide locking range

AbstractPeople’s requirement of speed and amount of communication grows with every passing since human steps in information era, which make communication technology become hot spot of technological development. Serial links has become the most popular transmission mode because of its advantages, such as high speed, long distance. Clock and data recovery (CDR) circuit is responsible for serial link systems to recovery clock and retime data. What’s more, with the increasing demand of speed and quality of communication, CDR restricts the speed and transmission quality of transmission, which makes it becomes as research focus and hot spots for scientists and engineers at present.This paper studies wide-band clock and data recovery circuit used in high-speed optical fiber communication systems. First, the research status of CDR is introduced, and the need for wide-band CDR circuits is discussed. Second, the different structures of clock and data recovery circuits are summarized and compared to decide which is suitable for wide-band used, and design a new circuit structure. Finally, we do system-level design including frequency band selector, low pass filter, new FD and PD.A 2Gbps to 8Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator (VCO), a frequency detector and a phase detector (FDPD) is described. A new automatic frequency band selection (FBS) without external reference clock is proposed to select the appropriate mode and also solve the instability problem when powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with four operation modes. The proposed CDR structure has been modeled with MATLAB and verified in the SMIC 180nm Mixed Signal Low Leakage RF 1.2/1.8/3.3V(1P2M ~ 1P9M) process in Hspice.Key words:Clock and Data Recovery Circuit, fiber-optical communication, Wide range lock, Frequency band selector目录摘要 ........................................................ IA