EDA 原理和应用实验.pdfVIP

8 ………………………………………….……...….……2 ………………………5 …………………………..………7 ………………………………………………..………10 …………………………………………………..………15 ………………………………………..………20 …………………………………………….……….32 2FSK ………………………………………….…..34 PCB ……..……………………….….35 ………………….………………………………36 1 8 1. MAX+plusII 2. GW48-CK EDA 3. VHDL 4 8 GW48-CK EDA EPF10K10LC84-3 1. 2. VHDL 3. 4. EDA 5. 6. EDA Max+PlusII VHDL 1) 4 ADDER4B.VHD LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY ADDER4B IS --4 PORT(C4 IN STD_LOGIC -- A4 IN STD_LOGIC_VECTOR(3 DOWNTO 0) --4 B4 IN STD_LOGIC_VECTOR(3 DOWNTO 0) --4 S4 OUT STD_LOGIC_VECTOR(3 DOWNTO 0) 4 CO4 OUT STD_LOGIC) -- END ENTITY ADDER4B 1 ARCHITECTURE ART OF ADDER4B IS SIGNAL S5STD_LOGIC_VECTOR(4 DOWNTO 0) SIGNAL A5B5 STD_LOGIC_VECTOR(4 DOWNTO 0) BEGIN A5=0 A4 --4 5 B5=0 B4 --4 5 S5=A5+B5+C4 S4=S5(3 DOWNTO 0) CO4=S5(4) END ARCHITECTURE ART 2) 8 ADDER8B.VHD LIBRARY IEEE USE IEEE.STE_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY ADDER8B IS -- 4 8 PORT(C8 IN STD_LOGIC A8 IN STD_LOGIC_VECTOR(7 DOWNTO 0) B8 IN STD_LOGIC_VECTOR(7 DOWNTO 0) S8OUT STD_LOGIC_VECTOR(7 DOWNTO 0) CO8 OUT STD_LOGIC) END ENTITY ADDER8B ARCHITECTURE ART OF ADDER8B IS COMPONENT ADDER4B IS