华南理工大学-数字逻辑（中文版）18-vhdl_dataflow_structural.pptVIP

Data Flow StructuralModeling of Combinational Logic Register Transfer Logic (RTL) Design Description Naming and Labeling (1) VHDL is not case sensitive Example: Names or labels databus Databus DataBus DATABUS are all equivalent Naming and Labeling (2) General rules of thumb (according to VHDL-87) All names should start with an alphabet character (a-z or A-Z) Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_) Do not use any punctuation or reserved characters within a name (!, ?, ., , +, -, etc.) Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid) All names and labels in a given entity and architecture must be unique Free Format VHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example: if (a=b) then or if (a=b) then or if (a = b) then are all equivalent Comments Comments in VHDL are indicated with a “double dash”, i.e., “--” Comment indicator can be placed anywhere in the line Any text that follows in the same line is treated as a comment Carriage return terminates a comment No method for commenting a block extending over a couple of lines Examples: -- main subcircuit Data_in = Data_bus; -- reading data from the input FIFO Comments Explain Function of Module to Other Designers Explanatory, Not Just Restatement of Code Locate Close to Code Described Put near executable code, not just in a header Signals signal A : std_logic; signal B : std_logic_vector(7 downto 0); Standard Logic Vectors Logic Operators Logic operators Logic operators precedence No Implied Precedence Wanted: Y = ab + cd Incorrect Y = a and b or c and d equivalent to Y = ((a and b) or c) and d equivalent to Y = (ab + c)d Correct Y = (a and b) or (c and d) Concatenation Rotations in VHDL Arithmetic Functions in VHDL (1) To use basic arithmetic operations