脉冲与数字电路课程设计报告--基于FPGA的数字钟.doc

计算机与信息工程系 《脉冲与数字电路》 课程设计报告 专业 ______ ____________ 班级 _____ ______________ 学号 _______________ 姓名_______________ 报告完成日期 ________ 指导教师 ____ ___________ 评语： 成绩： 批阅教师签名： 批阅时间： 基于FPGA的数字钟 摘 要 钟表是现代人类日常生活中必不可少的工具，数字钟更是现代社会时钟发展的一个重要方向。数字钟具有其突出的可随时控制调节时间、计时精确等优势和特点，被广泛地应用于社会生活的各个方面。本设计就是通过应用生活生产中常见的逻辑电路元件设计出具有计时和调时功能的数字钟。 本文主要从数字钟的设计原理、设计方案入手详细地介绍了数字时钟的硬件设计、软件设计和下载调试。在设计过程中要处理好以下几个关键方面：各种计数器、调节控制电路、显示器程序设计。计数器的设计关系到时钟计时的进位与精确度，调节控制电路是调节时间的关键。最后，利用QUARTUSⅡ仿真设计软件和设计开发板的特点和优势，结合实践，设计出具有基本调节控制功能的数字时钟。 关键词：数字钟，计数器，开发板，VHDL语言 Based on FPGA digital clock Abstract Clocks and watches is the modern human daily life essential tools, a digital clock is the development of modern society clock an important direction. A digital clock has its outstanding may at any time control regulation time, accurate timing advantages and characteristics, and is widely used in various aspects of their life. This design is through the application in production of the common life logic circuit components design has the function of the timing and when a digital clock. This article is mainly from the digital clock design principle, and the design of digital clock is introduced in detail the hardware design, software design and download debugging. In the design process to handle the following a few key aspects: all kinds of counter, adjust control circuit, monitor the program design. The design of the counter in relation to the clock binary and accuracy, adjust the control circuit is the key to regulating time. Finally, using QUARTUS Ⅱ simulation design software and design features and advantages of the development board, and combining the practice, the design has the basic regulation control functions of digital clock. Key words: a digital clock, counter, development board, VHDL language目　录 前　言 1 第1章 设计任务及要求 2 1.1设计任务及要求 2 1.1.1设计任务 2 1.1.2设计要求 2 第2章 设计原理 3 2.1 设计原理及结构框图 3 2.1.1设计原理 3 2.1.2系统结构框图 3 第3章 系统设计 4 3.1 VHDL硬件描述语言 4 3.1.1VHDL硬件描述语言简介 4 3.1.2VHDL硬件描述语言特点 4 3.2 用VHDL语言完成整个电