EDA改错题-副本.docVIP

指出下列程序设计元件的中文名，指出语法错误并改正，给出改正后的时序图： 1、 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;　USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4B ISPORT (CLK，RST，ENA: IN STD_LOGIC;OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT4B; ARCHITECTURE behav OF CNT4B ISSIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK, RST, ENA)BEGINIF RST = 1 THEN CQI = 0000;　　　　　　　0000ELSIF CLKEVENT AND CLK = 1 THENIF ENA = 1 THEN CQI = CQI + 1;　　　　　　　1ELSE CQI = 0000;END IF;　　　　　　　　　　　　　　　　　　　　　END IF;OUTY = CQI ;END PROCESS;COUT=CQI(0) AND CQI(1) AND CQI(2) AND CQI(3);END behav; 含异步清0和同步时钟使能的4位加法计数器 ２、 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8 ISPORT ( CIN : IN STD_LOGIC;A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);COUT : OUT STD_LOGIC_VECTOR );END ADDER8; ARCHITECTURE behav OF ADDER8 ISSIGNAL SINT : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); BEGINSINT　:=　(0 A) + B + CIN ; =S = SINT(7 DOWNTO 0); COUT = SINT(8);END behav; 8位硬件加法器 3、 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CLK_6D ISPORT (CLK,RST: IN STD_LOGIC; CLK_OUT: OUT STD_LOGIC);END CLK_6D; ARCHITECTURE ONE OF CLK_6D ISVARIABLE TEMP:STD_LOGIC; SIGNAL BEGIN PROCESS(CLK)VARIABLE CNT6D: INTEGER RANGE 0 TO 3;CONSTANT SIGN: INTEGER:=2; BEGINIF (RST = “1”) THEN TEMP = “0”; 　　　　1 , 0ELSIF CLKEVENT AND CLK=1 THEN 　　　 (CLKEVENT AND CLK=1) IF (CNT6D = SIGN) THENCNT6D := 0;TEMP = NOT TEMP;ELSE CNT6D := CNT6D+1;END IF;END IF;END PROCESS;CLK_OUT = TEMP; END ONE;六分频电路 电路时序图： 4、library ieee;use ieee.std_logic_1164.all; entity encoder isport (b: in std_logic(7 downto 0); b: in std_logic_vector(7 downto 0) y: out std_logic(2 downto 0)); 　　　y:out std_logic_vector(2 downto 0) end encoder; architecture one of encoder isbeginprocess (b)begincase b iswheny=111;wheny=110; wheny=101; wheny=100; when