Lecture 10 Vectors Coputer Science Division EECS at UC 讲座10载体计算机科学部是由加州大学.ppt

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Lecture 10 Vectors Coputer Science Division EECS at UC 讲座10载体计算机科学部是由加州大学.ppt

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Lecture 10 Vectors Coputer Science Division EECS at UC 讲座10载体计算机科学部是由加州大学

CS252Graduate Computer ArchitectureLecture 10Vector Processing (Continued)Branch Prediction October 4, 2000 Prof. John Kubiatowicz Review:Vector Processing Vector Processing represents an alternative to complicated superscalar processors. Primitive operations on large vectors of data Load/store architecture: Data loaded into vector registers; computation is register to register. Memory system can take advantage of predictable access patterns: Unit stride, Non-unit stride, indexed Vector processors exploit large amounts of parallelism without data and control hazards: Every element is handled independently and possibly in parallel Same effect as scalar loop without the control hazards or complexity of tomasulo-style hardware Hardware parallelism can be varied across a wide range by changing number of vector lanes in each vector functional unit. Review:ILP? Wherefore art thou? There is a fair amount of ILP available, but branches get in the way Better branch prediction techniques? Probably not much room to go still: prediction rates already up in the 93% and above Fundamental new programming model? Vector model accommodates long memory latency, doesn’t rely on caches as does Out-Of-Order, superscalar/VLIW designs: No branch prediction! Loops are implicit in model Much easier for hardware: more powerful instructions, more predictable memory accesses, fewer hazards, fewer branches, fewer mispredicted branches, ... But, what % of computation is vectorizable? Is vector a good match to new apps such as multimedia, DSP? Right answer? Both? Neither? (my favorite) Review: “DLXV” Vector Instructions Instr. Operands Operation Comment ADDV V1,V2,V3 V1=V2+V3 vector + vector ADDSV V1,F0,V2 V1=F0+V2 scalar + vector MULTV V1,V2,V3 V1=V2xV3 vector x vector MULSV V1,F0,V2 V1=F0xV2 scalar x vector LV V1,R1 V1=M[R1..R1+63] load, stride=1 LVWS V1,R1,R2 V1=M[R1..R1+63*R2] load, stride=R2 LVI V1,R1,V2 V1=M[R1+V2i,i=0..63] indir.(gather) CeqV VM,V1,V2 VMASKi = (V1i=V