Verplex Formal Solutionverpex形式解.pptVIP

Cadence Formal Verification2003 Beijing InternationalMicroelectronics Symposium Cadence Formal Overview Equivalence Checking (EC) Introduction Conformal SolutionComprehensive Equivalence Checking Solution Used throughout the implementation process Independently developed technology Production proven on 1000s of designs Best performance “Conformal by far blows away Formality in speed and capacity.” - Bob Lawrence, Agere Systems Conformal SolutionExtends EC to Complex Datapath Operator Merging Conformal SolutionProviding a Safer EC Environment Conformal Solution Clock Domain Checking Conformal Solution Semantic Checks Conditions that may create mismatches between RTL and gate-level simulations Full case Parallel case X-assignment Range Overflow Conformal checks if unexpected conditions can exist in design: s[1:0] == {0,0}, s[1,0] == {1,1} Finds functional mismatches that are otherwise missed or detected only by gate level simulation late in design cycle Equivalency can not find this type of error EC follows synthesis interpretation Conformal Solution Structural Checks Class of bugs typically found late in design cycle, if at all May not be present in “RTL” , scan insertion errors Introduced during design integration Introduced during implementation and ECOs Bus Checks Bus contention Bus or net driven by conflicting data Bus floating Bus is not driven by any signal Tri-state Stuck-at problem with tri-state driver enable Set / Reset Check Set and Reset on at the same time Multi-port Latch Check Multi-port latches loaded with conflicting values Conclusion The verification problem continues to grow at an exponential rate Simulation-based techniques cannot meet the challenge alone Formal analysis is a critical requirement for thorough verification Equivalence checking is used throughout the implementation process Conformal offers the only comprehensive EC solution for complex SoCs Conformal technology was developed independently to maintain verification integ