Final Exam Project - Home Department of Computer 期末考试项目-计算机家系.pptVIP

4 Bit Full Adder Simulation- A1+B1 (Cont’d) 4 Bit Full Adder Simulation- A2+B2 (Cont’d) 4 Bit Full Adder Simulation- A3+B3 (Cont’d) Related Documents Included floppy contains two directories LASI and CIR. LASI Directory Contains all the Layout files and other required files to open layouts in LASI . To open LASI Layout files create shortcut of LASI executable file, and change the “Start in” option through properties to A:\ LASI \. Circuit simulation .CIR files are located in CIR directories. Final Exam Project 4 bit Full Adder Layout and Analysis using Lasi and WinSpice Assignment Objectives Do a hierarchal layout of a half adder, full adder and 4 bit adder using LASI, then simulate the circuit using SPICE to make sure that the design will work. Overview Hierarchal Layout design is done using Lasi. N3X2, P3X2, NAND, XOR, Half-Adder, Full-Adder and 4 bit Full Adder layouts are made in hierarchal sfashion using bottom up approach. Each Cell is analyzed by using Winspice3 .CIR file created by Lasi. P3X2 (Rank 1)Cell- Standard cell from Lasi Library N3X2 (Rank 2) Cell -Standard cell from Lasi Library INVERTER (Cont’d) Inverter cell has Rank 2. Inverter cell is made using P3X2 and N3X2 cell. It is used to provide A’ and B’ for XOR input and NAND input to make OR gate.Also it is used at output of a NAND to make AND. INVERTER NAND (Cont’d) NAND cell has rank 2. It is used to make AND gate and OR gate. NAND XOR (Cont’d) XOR cell has Rank 2. It is is made to provide sum of Half Adder. It is little different than regular XOR because it requires four inputs A, A’, B, and B’. By designing in with four inputs we simplify design and reduced transistors. XOR Half-Adder (Cont’d) Half-Adder has rank 3. It is designed using INVERTER, NAND and XOR gate. Sum = AB’ + B’A. Carry = AB. Half-Adder Full-Adder (Cont’d) It has rank 4. Full adder is made using two HALF-ADDER , 2 Inverter and a NAND gate. S1 = HA(A,B) Sum = HA(S1,Carry In) Carry = OR(Carry 1,Carry 2) F