EE 447 VLSI Design Lecture 8 Combinational CircuitsEE 447组合电路的VLSI设计讲座.pptVIP

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EE 447 VLSI Design Lecture 8 Combinational CircuitsEE 447组合电路的VLSI设计讲座.ppt

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EE 447 VLSI Design Lecture 8 Combinational CircuitsEE 447组合电路的VLSI设计讲座

EE 447 VLSI DesignLecture 7: Combinational Circuits Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgan’s Law Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. Compound Gates Logical Effort of compound gates Compound Gates Logical Effort of compound gates Example 4 The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. Example 4 The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. NAND Solution NAND Solution Compound Solution Compound Solution Example 5 Annotate your designs with transistor sizes that achieve this delay. Example 5 Annotate your designs with transistor sizes that achieve this delay. Input Order Our parasitic delay model was too simple Calculate parasitic delay for Y falling If A arrives latest? If B arrives latest? Input Order Our parasitic delay model was too simple Calculate parasitic delay for Y falling If A arrives latest? 2? If B arrives latest? 2.33? Inner Outer Inputs Outer input is closest to rail (B) Inne