第一讲 流水线数据通路与控制逻辑第二讲 流水线冒险处理第.ppt

Here are the timing diagrams showing the differences between the single cycle, multiple cycle, and pipeline implementations. For example, in the pipeline implementation, we can finish executing the Load, Store, and R-type instruction sequence in seven cycles. In the multiple clock cycle implementation, however, we cannot start executing the store until Cycle 6 because we must wait for the load instruction to complete. Similarly, we cannot start the execution of the R-type instruction until the store instruction has completed its execution in Cycle 9. In the Single Cycle implementation, the cycle time is set to accommodate the longest instruction, the Load instruction. Consequently, the cycle time for the Single Cycle implementation can be five times longer than the multiple cycle implementation. But may be more importantly, since the cycle time has to be long enough for the load instruction, it is too long for the store instruction so the last part of the cycle here is wasted. +2 = 77 min. (X:57) The solution we have is to AND the write enable signal to the clock input. The Write Enable signal to register file or memory is probably the ONLY place where you as a logic designer can gate (AND) the clock with a control signal. This is the place where you need to take off your logic designer’s hat and put on an electrical engineer’s hat to make sure by ANDING the write enable signal to the clock signal, you are NOT violating any timing consideration. One obvious thing you should check is that the clock high time must be greater than the write access time because the C_WrEn signal will only be high during the clock high time. After the circuit designer have taken a good look at this block and make sure no timing constraint is violated, he or she will create a symbol like this and give it to the logic designer. And he probably will tell the logic designer something like: “Hey, don’t change anything in this block without first asking me.” The logic designer can then us