定时器A寄存器.docVIP

寄存器 缩写Timer_A Control TAxCTLTimer_A Capture/Compare Control 0 TAxCCTL0Timer_A Counter TAxRTimer_A Capture/Compare 0 TAxCCR0Timer_A Interrupt Vector TAxIVTimer_A Expansion 0 TAxEX0Timer_A Control Register (TAxCTL)UnusedTASSELIDMCUnusedTACLRTAIETAIFGTASSEL Bits 9-8 Timer_A clock source select 00 TAxCLK01 ACLK10 SMCLK11 Inverted TAxCLKID Bits 7-6 Input divider. These bits along with the IDEX bits select the divider for the input clock00 /101 /210 /411 /8MC Bits 5-4 Mode control00 Stop mode: Timer is halted01 Up mode: Timer counts up to TAxCCR010 Continuous mode: Timer counts up to 0FFFFh11 Up/down mode: Timer counts up to TAxCCR0 then down to 0000hTACLR Bit 2 Timer_A clearSetting this bit resets TAxR, the timer clock divider, and the count direction. The TACLR bit is automatically reset and is always read as zero.TAIE Bit 1 Timer_A interrupt enable0 Interrupt disabled1 Interrupt enabledTAIFG Bit 0 Timer_A interrupt flag0 No interrupt pending1 Interrupt pendingTimer_A Counter Register (TAxR) 计数 寄存器 ： 写入初值 然后开始 自增/自减 到达一定值后 溢出 发出中断Capture/Compare Control Register (TAxCCTL0)CMCCISSCSSCCIUnusedCAPOUTMODCCIECCIOUTCOVCCIFGCM Bits 15-14 Capture mode00 No capture01 Capture on rising edge10 Capture on falling edge11 Capture on both rising and falling edgesCCIS Bits 13-12 Capture/compare input selectThese bits select the TAxCCRn input signal. See the device-specific data sheet for specific signal connections 00 CCIxA01 CCIxB10 GND11 VCCSCS Bit 11 Synchronize capture source0 Asynchronous capture1 Synchronous captureSCCI Bit 10 Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and c