(EDA技术实用教程第2版)第5章_VHDL设计进阶.ppt

【 WHEN 001 = REG(0) = C0 ; REG(7 DOWNTO 1) = REG(6 DOWNTO 0); CY = REG(7);--带进位循环左移 WHEN 010 = REG(0) = REG(7); REG(7 DOWNTO 1) = REG(6 DOWNTO 0); --自循环左移 WHEN 011 = REG(7) = REG(0); REG(6 DOWNTO 0) = REG(7 DOWNTO 1); --自循环右移 WHEN 100 = REG(7) = C0 ; REG(6 DOWNTO 0) = REG(7 DOWNTO 1); CY = REG(0); --带进位循环右移 WHEN 101 = REG(7 DOWNTO 0) = D(7 DOWNTO 0); --加载待移数 WHEN OTHERS = REG = REG ; CY = CY ; --保持 END CASE; END IF; END PROCESS; QB(7 DOWNTO 0) = REG(7 DOWNTO 0); CN = CY; --移位后输出 END BEHAV; 接上页 5.3.4 进程中的信号与变量赋值语句 5.3 数据对象DATA OBJECTS 图5-