超高频rfid阅读器中σδfractional-npll频率综合器的设计-design of σ δ fractional - npll frequency synthesizer in uhf rfid reader.docxVIP

ABSTRACTThe ever growing need for convenient and portable wireless communication equipment demands high performance and low cost wireless transceiver. This thesis discusses the research on the RF frequency synthesizers, the critical building block in modern wireless transceivers. The phase noise model of phase-locked loop (PLL) frequency synthesizer is derived and analyzed. It also sums up VCO phase noise model. Fast frequency correction technology for frequency synthesizer is studied in-depth and this paper also proposes corresponding improved method. More specific contents are as follows:Fir