soc设计方法与实现第8章综合与sta.pptVIP

第八章 综合策略及静态时序分析 Outlines Logic Synthesis Compiling Strategy Physical Synthesis Compiling Strategy Synthesis Using Synopsys’s Design Compiler (DC) Static Timing Analysis (STA) STA Using Synopsys’s Primetime (PT) Statistical Static Timing Analysis (SSTA) What Logic Synthesis Do? Selecting and Using a Compiling Strategy Compiling Strategy: Top-down The top-level design and all its sub design are compiled together Advantages: Only top level constraints are needed Better results due to optimization across entire design Disadvantages Long compile times Incremental changes to the sub-blocks require complete re-synthesis Tool limit for handle “large” design Compiling Strategy： Bottom-up The individual sub designs are compiled separately You may need to do Time-budgeting at top level to get constraint file for each sub design Starting from the bottom of the hierarchy and proceeding up through the levels of the hierarchy until the top-level design is compiled Compiling Strategy： Bottom-up – cont. Advantages Easier to manage the design because of individual scripts Good quality results in general because of flexibility in targeting and optimizing individual blocks Disadvantages Tedious to update and maintain multiple scripts Critical paths seen at the top level may not be critical at lower level Optimizing Design Architectural optimization e.g. Selecting DesignWare implementations Logic-Level optimization Structuring -- for reduced design area Flattening -- for speed optimization Gate-Level optimization Delay optimization Design rule fixing Area optimization Timing correction is most effective with placement information E.g., Physical synthesis Large Circuit Optimization Problems Run-time becomes intractable Quality of solution drops sharply Suggestion Circuit partition – using bottom-up synthesis strategy “Timing budget” synthesis strategy Top-down (RTL-to-gate) to get the timing budget for each module, then do synthesis optimization on each module, followed by gat