一个VHDL设计由若干个VHDL文件构成每个文件主要包含.pptVIP

第 5 章 VHDL语言的主要描述语句 1) 多数决定的数字滤波器（4位） 滤波器输出信号d_f的取值由滤波器输入信号前 N次采样值表决而定，原则是多数取胜。假定采 样次数N为3，若 (d_in(N-2)+d_in(N-1)+d_in≥2 则d_f的取值为‘1’，否则为‘0’。 提示：设计要利用数组和循环语句。 见文件 majority.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity majority is port (clk,resetn: in std_logic; d_in: in std_logic_vector(3 downto 0); d_f : out std_logic_vector(3 downto 0)); end; architecture rtl of majority is type array_4 is array(3 downto 0)of std_logic_vector(2 downto 0); signal s_d:array_4; signal d_f_i:std_logic_vector(3 downto 0); begin process(clk,resetn) begin if resetn=0 then for i in 0 to 3 loop s_d(i)=000; end loop; elsif clkevent and clk=1then for i in 0 to 3 loop s_d(i)(0)=d_in(i); for j in 0 to 1 loop s_d(i)(j+1)=s_d(i)(j); end loop; end loop; end if; end process; 该进程完成将三位数并行读入 process (s_d) type array_42 is array(3 downto 0)of std_logic_vector(1 downto 0); variable ct:array_42; begin for i in 0 to 3 loop ct(i) :=(0s_d(i)(2))+(0s_d(i)(1))+(0s_d(i)(0)); if ct(i)=2 then d_f_i(i)=1; else d_f_i(i)=0; end if; end loop; end process; 该进程完成输出数据计算 process (clk,resetn) begin if resetn=0 then d_f=(others=0); elsif clkevent and clk=1 then d_f=d_f_i; end if; end process; end; 该进程完成输出赋值 2) 二进制转换为格雷码（8位） 提示：设二进制码为A=a7a6a5a4a3a2a1a0 格雷码为Y=y7y6y5y4y3y2y1y0 则：y7=a7 ; yi=ai+1 ai ; i≠7 见文件： bintogray.vhd library ieee; use ieee.std_logic_1164.all; entity bintogray is port (a: in std_logic_vector(7 downto 0); y: out std_logic_vector(7 downto 0)); end; architecture rtl of bintogray is begin process (a) variable tmp:std_logic_vector(7 downto 0); begin tmp(7):=a(7); for i in 6 downto 0 loop tmp(i):=a(i) xor a(i+1); end loop; y=tmp; end process; end rtl; 3) 设计一个乘常数的电路 从资源和速度考虑，常系数乘法运算可用移