VHDL数据型(vhdl语法).ppt

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity full_bit_adder is port(a,b,ci:in std_logic; y,cout:out std_logic); end full_bit_adder; architecture bh1 of full_bit_adder is begin y = ((not a)and (not b)and ci) or ((not a)and (b) and (not ci)) or ((a)and (not b)and(not ci)) or ((a) and (b)and(ci)); cout = (b and ci) or (a and ci) or (a and b); end bh1; architecture bh2 of full_bit_adder is begin y = a xor b xor ci; cout = (a and b) or (a and ci) or (b and ci); end bh2; con