2VHDL计初步1.ppt

LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FullAdder is PORT(A,B,C: IN Std_Logic; CY : OUT Std_Logic； S : OUT Std_Logic); END FullAdder; ARCHITECTURE a OF FullAdder IS BEGIN S = A Xor B Xor C; CY = (A and B) OR (A and C) OR (B and C); End a; A B S CY C 4位串行进位加法器 用例化语句实现4位串行进位加法器。 ENTITY Adder_4 is PORT( A ,B: IN Std_Logic_Vector(3 Downto 0); S : OUT Std_Logic_Vector(3 Downto 0); C : INOUT Std_Logic_Vector(4 Downto 0) ); END Adder_4; Full Adder Full Adder Full Adder Full Adder S(3) S(2) S(1)