课程名称-交大资工.PPT

Lab 1 and 2:Digital System Design Using Verilog Ming-Feng Chang CSIE, NCTU Introduction Objectives Understand the design methodologies using Verilog Target audience have basic digital circuits design concept use Verilog to design digital systems Verilog description for logic synthesis NOT in the talk a full coverage of Verilog use Verilog for quick behavioral modeling Contents Verilog HDL structured modeling RTL modeling Example combinational circuits structured description (net-list) RTL Example sequential circuits RTL FSM combinational circuits sequential circuits Verilog history Gateway Design Automation Phil Moorby in 1984 and 1985 Verilog-XL, XL algorithm, 1986 a very efficient method for doing gate-level simulation Verilog logic synthesizer, Synopsys, 1988 the top-down design methodology is feasible Cadence Design Systems acquired Gateway December 1989 a proprietary HDL Open Verilog International (OVI), 1991 Language Reference Manual (LRM) making the language specification as vendor-independent as possible. The IEEE 1364 working group, 1994 to turn the OVI LRM into an IEEE standard. Verilog became an IEEE standard December, 1995. Hardware Description Languages The functionality of hardware concurrency timing controls The implementation of hardware structure net-list ISP C. Gordon Bell and Alan Newell at Carnegie Mellon University, 1972 RTL (register transfer level) Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate gate-level net-list Switch transistor-level net-list Verilog for Digital System Design Structural description net-list using primitive gates and switches continuous assignment using Verilog operators RTL functional description timing controls and concurrency specification procedural blocks (always and initial) registers and latches C + timing controls + concurrency An HDL to specify your design Hierarchical structure Represent the hierarchy of a de