2014全国大学生电子设计竞赛2-Training Lab_IPC.docx

College Contest Training Lab2 – Inter-core Communication In IPCGR and QMSS Purpose The purpose of this lab is to demonstrate how to use IPCGR and QMSS for inter-core sync and communication. It can be used as a basic multicore project for multicore architecture reference. The detailed operation guide and snapshot will help user for better understanding. In this lab, we use CCS v5.4.0.00091 and EVM6657 as the example for the following demonstration. Backup: Multicore Example Architecture 1) Select one core as master, responsible for the PLL and DDR initialization. Core0 is set as the master here; 2) Use IPCGR for multicore sync to ensure the PLL and DDR initialization has finished before the following process; 3) After initialization sync, each core configures its memory property such as the cache attributes, and process its application respectively. 4) For some applications, maybe there is message communication between cores, QMSS is used in the example. For more knowledge about QMSS refer to the Multicore Navigator slides and user guide. Task 1: Import the Project 1) Click “File”-“Import” 2) Choose the correct “Input Source Type” then click “Next” 3) Choose “Select search-directory”, then “Browse” the folder your project located then click “OK” 4) Select the project you want to import and click “Finish” to finish the import procedures 5) Then you’ll see the imported project on CCSv5 Task 2: Build CCS Project 1) Before build your CCS project, please make sure to check the file path, especially for the linked files (files not in the original project folder) and relative path. Please make sure there is no yellow “!” on linked files. If there is “!” on the linked files, just remove and add it again. The macros and relative path for linked files are defined in: 2) The header file search path can be edited and added in the compiler-include options as below. Here the csl header file search path should be edited based on the pdk install path. The lib search path can be a