RISC CPU的数字系统逻辑设计毕业设计论文.doc

中 文 摘 要 PAGE 毕业设计（论文） 题 目：RISC CPU的数字系统逻辑设计 专 业： 计算机科学与技术 院（系）： 信息工程学院 RISC CPU的数字系统逻辑设计 摘 要：RISC即精简指令集计算机（Reduced Instruction Set Computer）的缩写。RISC-CPU与一般的CPU相比，通过简化指令系统使计算机的结构更加简单合理，从而提高了运算速度。本文对RISC-CPU的架构进行了分析，并使用Verilog语言设计了8位RISC-CPU IP软核。 RISC-CPU由八大基本模块构成：时钟发生器、指令寄存器、累加器、算术逻辑单元、数据输出控制器、地址多路器、程序计数器、状态控制器。本设计中借助Quartus II软件平台对各模块进行时序仿真，并最终给出了指令执行的仿真波形，验证了CPU的功能。 设计仿真结果表明，该8位RISC-CPU能够完成既定的任务指标，而且在运行效率上有一定程度改善。 关键词：RISC-CPU、Verilog、Quartus II、时序仿真 Abstract Abstract :RISC reduced instruction set computer that (Reduced Instruction Set Computer) acronym. RISC-CPU and CPU in general compared to instruction by simplifying the structure of the computer is more simple and reasonable, thereby increasing processing speed. In this paper, RISC-CPU architecture is analyzed, and by using the Verilog language, I designed an 8-bit RISC-CPU IP soft core. RISC-CPU is based on 8 modules: clock generator, instruction register, accumulator, arithmetic logic unit, data output controller, address multiplexer, program counter, state controller. In the design, each module are timing simulated on Quartus II software platform, and finally the simulated waveform of instruction execution that verifies the CPU features is given. Design and simulation results show that the 8-bit RISC-CPU can complete the tasks, and also has a certain degree of improvement on operational efficiency. Keywords: RISC-CPU, Verilog, Quartus II, Timing Simulation 目 录 目 录 TOC \o 1-3 \h \z \u HYPERLINK \l _Toc295176393 摘 要 PAGEREF _Toc295176393 \h I HYPERLINK \l _Toc295176394 Abstract（英文摘要） PAGEREF _Toc295176394 \h II HYPERLINK \l _Toc295176395 目 录 PAGEREF _Toc295176395 \h III HYPERLINK \l _Toc295176396 第一章 前言 PAGEREF _Toc295176396 \h 1 HYPERLINK \l _Toc295176397 1.1 课题背景 PAGEREF _Toc295176397 \h 1 HYPERLINK \l _Toc295176398 1.1.1 什么是CPU？ PAGEREF _Toc295176398 \h 1 HYPERLINK \l _Toc295176399 1.1.2 什么是RISC-CPU？ PAGEREF _Toc295176399 \h 1 HYPERLINK \l _To