动态随机存储器(DRAM)的BIST设计研究-测试计量技术与仪器专业论文.docx

摘 要 DRAM 产品被视为半导体工业的技术引擎，因此，高质量的测试策略显得尤为 重要。BIST（Built-In Self-Test，内建自测试）作为一种可以全速测试的 DFT（Design For Testability,可测性设计）解决方案被广泛应用于存储器测试。March 测试算法因其 较高的故障覆盖率及较低的复杂度而成为存储器测试的常用算法。 本文在认真研究了 DRAM 故障模型和 March 算法的基础上，设计了两种指令编 码规则，一种是为了实现对面向 DRAM 特有故障的测试算法的编码，另一种则是为 了实现对面向存储器普通故障的测试算法的编码。 本文设计了一种基于指令的 DRAM BIST 控制器，该控制器能够兼容两种指令编 码，以满足对 DRAM 中特有故障和存储器普通故障的测试。它有四种工作模式，每 种工作模式适合不同的测试要求。 为了支持不同算法及不同类型 DRAM 的测试，本文以 DRAM BIST 控制器为基 础设计了一个 DRAM BIST IP 核自动生成系统，该系统能够根据用户定义的相关参数 自动生成 DRAM BIST IP 软核，以满足不同的测试需要。 经实验表明，本文设计的 DRAM BIST IP 核能够实现对 DRAM 中存在的特有故 障以及存储器普通故障的测试，基本达到实用化的程度，具有较好的应用前景。 关键词： BIST，DRAM，指令编码，控制器，自动生成 Study on the DRAM BIST Design ABSTRACT DRAM is regarded as the engine of semiconductor technique,so effective test method is very important. BIST(Built-In Self-Test) is an at-speed test method of DFT(Design For Testability) which is used to test memory. March test is generally adopted in memory BIST because of lower complication and better fault coverage. In this paper, DRAM fault models and March tests were studied in detail. Two types of instruction codes are designed. One is to accomplish coding on the March algorithms which are used to test DRAM specific faults. The other is to accomplish coding on the March algorithms which are used to test the memory generic faults of DRAM. In this paper a DRAM BIST controller based on instruction is designed. This is compatible to two types of instructions in order to meet with test requirement for specific faults and generic faults of DRAM. This controller has four work modes, and each mode can meet with different test requirement. Basing on the DRAM BIST controller and the parameters defined by user, a system of automatic generation of DRAM BIST IP core is designed. The system can generate DRAM BIST IP softcores based on users defining of DRAM and March test. The verification results show that the DRAM BIST IP core can test specific faults and generic faults of DRAM. It can be put into practical use, and has preferable adhi