CMOS集成电路-反相器.pptVIP

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CMOS集成电路-反相器.ppt

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CMOS集成电路-反相器.ppt

Technology Evolution (2000 data) International Technology Roadmap for Semiconductors 186 177 171 160 130 106 90 Max mP power [W] 1.4 1.2 6-7 1.5-1.8 180 1999 1.7 1.6-1.4 6-7 1.5-1.8 2000 14.9 -3.6 11-3 7.1-2.5 3.5-2 2.1-1.6 Max frequency [GHz],Local-Global 2.5 2.3 2.1 2.4 2.0 Bat. power [W] 10 9-10 9 8 7 Wiring levels 0.3-0.6 0.5-0.6 0.6-0.9 0.9-1.2 1.2-1.5 Supply [V] 30 40 60 90 130 Technology node [nm] 2014 2011 2008 2004 2001 Year of Introduction Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm Technology Evolution (1999) ITRS Technology Roadmap Acceleration Continues Technology Scaling (1) Minimum Feature Size Technology Scaling (2) Number of components per chip Technology Scaling (3) Propagation Delay tp decreases by 13%/year 50% every 5 years! Technology Scaling (4) From Kuroda Technology Scaling Models Scaling Relationships for Long Channel Devices Transistor Scaling(velocity-saturated devices) mProcessor Scaling P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001 mProcessor Power P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001 mProcessor Performance P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001 2010 Outlook Performance 2X/16 months 1 TIP (terra instructions/s) 30 GHz clock Size No of transistors: 2 Billion Die: 40*40 mm Power 10kW!! Leakage: 1/3 active Power P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001 Some interesting questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process Variation EE141 * Delay Formula Cint = gCgin with g ? 1 f = CL/Cgin - effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit Apply to Inverter Chain CL In Out 1 2 N tp = tp1 + tp2 + …+ tpN Optimal Tapering for Given N Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N Minimize the delay, find N - 1 partial derivatives Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 Size of each stage is the geometric mean of two neighbors each