高速模拟乘法器及高速fpga逻辑的仿真研究-电子与通信工程专业论文.docxVIP

摘要I 摘要 I 摘要 高速模拟和数字电路作为集成电路的主要组成形式，其性能优劣对集成电路 能否高效运行有着极大的影响，进行相关问题的仿真研究对实际工程的应用具有 重要意义。本文主要以数字预失真系统为依据进行仿真研究。 在高速模拟乘法器部分，本文首先介绍了模拟乘法器的基本原理，阐述了 BJT(Bipolar Junction Transistor)和 MOS(Metal-Oxide-Semiconductor)两种不同工艺 结构模拟乘法器的组成，并对其进行了相应的仿真研究，将两者的性能进行了比 较。 在高速 FPGA 逻辑电路部分，本文针对工作频率高且复杂的设计中存在的时 序瓶颈问题进行了仿真研究。首先介绍了时序的基本理论知识，然后根据实际存 在的时序问题，通过综合选项设置、代码优化、约束添加以及相关 EDA(Electronic Design Automatic)工具的使用，最终达到了时序收敛。 关键词：模拟乘法器 FPGA 数字预失真 静态时序分析 ABS ABSTRACT III ABSTRACT As the main form of integrated circuit，the performance of high speed analog and digital circuit have a great influence on the efficient operation of integrated circuit. The simulation research on related problems of practical engineering application has important significance.This thesis mainly study on the system of digital predistortion. As part of high speed analog multiplier,this thesis firstly introduced the analog multiplier principle, elaborated the diffierent technological structure of BJT(Bipolar Junction Transistor) and MOS(Metal-Oxide-Semiconductor) analog multiplier, carried on the corresponding simulation research and the performance comparison. As part of high speed FPGA logic circuits,a simulation research of sequential bottleneck problem in high working frequency and complex design has been realized.The thesis introduced the timing related basic theories, and by using a comprehensive set of options, code optimization, constraints and associated tools of EDA (Electronic Design Automatic), the timing convergence was finally achieved. Key words: Analog Multiplier Field-Programmable Gate Array Digital Predistortion Static Timing Analysis 专有名词对照表 专有名词对照表 V 专有名词对照表 EDA Electronic Design Automatic 电子设计自动化 IC Integrated Circuit 集成电路 SoC System On Chip 片上系统 ADC Analog Digital Converter 数模转换器 RF Radio Frequency 无线电频率 CMOS Comlementary Metal-Oxide-Semiconductor Transistor 互补金属氧化物半导体 BJT Biplor Junction Transitor 双极型晶体管 ASIC Application Specific Integrated Circuit 专用集成电路 CPLD Complex Programmable Logic Device 复