IS42S32160A-75B;IS42S32160A-75BI;IS42S32160A-75BL-TR;中文规格书,Datasheet资料.pdf

IS42S32160A-75B;IS42S32160A-75BI;IS42S32160A-75BL-TR;中文规格书,Datasheet资料.pdf

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IS42S32160A 4M Words x 32 Bits x 4 Banks (512-MBIT) PRELIMINARY INFORMATION SYNCHRONOUS DYNAMIC RAM JULY 2009 FEATURES · Concurrent auto precharge DESCRIPTION · Clock rate: 133 MHz · Fully synchronous operation The ISSI IS42S32160A is a high-speed CMOS · Internal pipelined architecture configured as a quad 4M x 32 DRAM with a synchronous interface (all signals are registered on the · Four internal banks (4M x 32bit x 4bank) positive edge of the clock signal,CLK). · Programmable Mode -CAS#Latency:2 or 3 It is internally configured by stacking two 256Mb, -Burst Length:1,2,4,8,or full page 16 Meg x 16 devices. Each of the 4M x 32 bit banks is organized as 8192 rows by 512 columns by 32 bits. -Burst Type:interleaved or linear burst Read and write accesses start at a selected locations · Burst stop function in a programmed sequence. Accesses begin with · Individual byte controlled by DQM0-3 the registration of a BankActive command which is · Auto Refresh and Self Refresh then followed by a Read or Write command. · 8K refresh cycles/64ms

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