基于vhdl语言成功数字钟源程序设计说明书.docx

PAGE 40 PAGE 39 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count2 is port(clk:in std_logic; output:out std_logic_vector(2 downto 0)); end; architecture shi of count2 is signal A :std_logic_vector(2 downto 0); begin process(clk) begin if clkevent and clk=1 then if A=111 then A=000; else A=A+1; end if; end if; end process; output=A; end; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fenping is port(clock:in std_logic; Q:out std_logic); end; architecture fenpin of fenping is signal full:std_lo