应用移位相加原理设计8位乘法器.DOC

应用移位相加原理设计8位乘法器 顶层文件 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity multi8x8 is port(clkk,start:in std_logic; a,b:in std_logic_vector(7 downto 0); dout:out std_logic_vector(15 downto 0)); end entity; architecture struc of multi8x8 is component arictl port(clk,start:in std_logic; clkout,rstall:out std_logic); end component; component andarith port(abin:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(7 downto 0)); end component; component adder8b port(cin:in std_logic; a,b:in std_logic_vector(7 downto 0); s:out std_logic_vector(7 downto 0); cout:out std_logic); end component; component sreg8b port(clk,load:in std_logic; din:in std_logic_vector(7 downto 0); qb:out std_logic); end component; component reg16b port(clk,clr:in std_logic; d:in std_logic_vector(8 downto 0); q:out std_logic_vector(15 downto 0)); end component; signal gndint,intclk,rstall,newstart,qb:std_logic; signal andsd:std_logic_vector(7 downto 0); signal dtbin:std_logic_vector(8 downto 0); signal dtbout:std_logic_vector(15 downto 0); begin dout=dtbout; gndint=0; process(clkk,start) begin if(start=1)then newstart=1; else if(clkk=0)then newstart=0; end if; end if; end process; u1:arictl port map(clk=clkk,start=newstart,clkout=intclk,rstall=rstall); u2:sreg8b port map(clk=intclk,load=rstall,din=b,qb=qb); u3:andarith port map(abin=qb,din=a,dout=andsd); u4:adder8b port map(cin=gndint,a=dtbout(15 downto 8),b=andsd,s=dtbin(7 downto 0),cout=dtbin(8)); u5:reg16b port map(clk=intclk,clr=rstall,d=dtbin,q=dtbout); end architecture; 各部件 arictl—控制元件 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity arictl is port(clk,start:in std_logic; clkout,rstall:out std_logic); end entity; architecture bhv of arictl is signal cnt4b:std_logic_vector(3 downto 0); begin process(clk,start) begin rstall=start; if(start=1)then cnt4b=0000;