华南理工大学《数字系统设计》2018年《数字系统设计》试卷a部分答案知识课件.pptxVIP

4．按要求转换下列程序。 （1） WAIT UNTIL clock’EVENT AND clock=‘1’; q = data; （2）If a(3)=1 then Y=”11”; Elsif a(2)=1 then Y=”10”;Elsif a(1)=1 then Y=”01”; Else Y= 00 ;End if; ;Answer whether each of the VHDL code has the same behaviour as the timing diagram Notes: 1)”same behaviour” means that the signals a,b,and c have the same values at the end of each clock cycle in steady-state simulation(ignore any irregularities in the first few clock cycles) 2)for full marks, if the code does not match, you must explain why. 3) assume that all signals, constrants, variables, types, etc are prop