低资源高速度FIR滤波器设计及其FPGA实现-物理电子学专业论文.docx

Abstract As a basic function unit of digital signal processing, finite impulse response (FIR) digital filters have advantages of stability, linear-phase, arbitrary amplitude, design flexibility. It has been widely used in many fields such as communication, radar, image processing and speech processing. Traditionally，the hardware used for real time implementation of FIR filter mainly include MCU、DSP and ASIC,etc. In practical applications, the characteristics of real-time、high-speed and flexibility are required for signal processing. However, most of the traditional hardware and software techniques which are available for the implementation of FIR filter are difficult to satisfy all of these requirements at the same time. With the development of PLD device and EDA technologies, FPGA has the characteristics of flexible programmable logic which can be conveniently used for implementing real-time digital signal processing, because it break through the level limit of parallel processing and pipeline technology. The resource of FPGA can be utilized effectively because it has the characteristic of reconfigurable logic resource on chip. More and more researchers who engage in digital signal processing are favoring FPGA. The paper mainly do study on the implementation of FIR filter targeted FPGA with the purpose of reducing system resource consumption、improving system processing speed and improving resource utilization rate. We mainly start the work on the development method and algorithm structure to reach the aims. The main works carried out in this paper are as follows: The methods of designing FIR filter which are based on SYSGEN and DA are introduced in this paper. Appropriate method of implementing FIR filter targeted FPGA is studied on the basic of the thoery of FIR filter design and FPGA implementation. In order to solve the promblems of too much resource consumption、too low processing speed and too low resource utilization rate using the traditional S