基于SOPC的JPEG2000静止图像编码器设计信息与通信工程专业论文.docxVIP

Abstract In the field of digital image compression, JPEG is the most popular standard. However, with the increasingly application of high-quality digital image, JPEG has been unable to meet the need of people. So, the Joint Photographic Experts Group developed a new generation of image compression standard – JPEG2000. Comparing with JPEG, JPEG2000 provides a better compression performance and more functions, which will make it mainstream in the future. However, with its complex coding process, JPEG2000 is seldom used in the embedded field, which limits the commercial application in some way. With the rapid development of FPGA devices, the concept of system on a programmable chip (SOPC) came into being. SOPC integrates function modules which are often used in system designing such as processor, memorie, and I/O on single FPGA chip. Designers could use HDL languages to implement modules whose computation amount is large, and use software to implement modules whose control logic is complex, so as to truly realize the software/hardware co- design, greatly enhance the flexibility of the system and reduce the difficulty of development. Therefore, SOPC is a good choice of implementing JPEG2000 encoder in embedded system. This dissertation first researched the principle of and coding processes of JPEG2000, carefully analysed the features of the key technology, such as pre- process, wavelet transform, entropy coding and code stream organization. Then proposed a VLSI architecture of two-dimensional discrete wavelet transform. The architecture uses pipeline and line-based technique, makes full use of the parallel characteristics of FPGA, and greatly reduces the transforming time and the amount of memory. At the clock frequency of 50MHz, the architecture could finish 4-level wavelet transform of a 8-bit greyscale picture with the size of 512 by 512 in 13.2ms, and the memory consumption is only 20KB, which can be met with the memory inside Mid-range FPGAs. Next, this dissertati