基于UVM的RFID非接触卡系统级验证-软件工程专业论文.docxVIP

摘要 随着集成电路规模和复杂度的提高，验证的工作量以指数形式增加。功能验 证作为保证集成电路功能正确的重要环节，面临着重大挑战，需要新的验证技术 来提高验证能力。基于 SystemVerilog 语言的 UVM 验证方法学可以提高验证效率。 SystemVerilog 语言的验证方面特性，可以提高验证平台的抽象层次和复用性， 满足验证对于语言功能的需求。本文对 UVM 的验证架构以及主要组件 UVC 的分 类，结构，功能进行研究。同时，分析了 UVM 标准类库中各基类的继承关系。 UVM 方法学利用 SystemVerilog 语言构建的标准类库充分发挥了语言的验证能力。 本文的验证对象是一款 RFID 非接触卡，如何利用 UVM 的思想方法，搭建出 RFID 卡的系统级验证环境，提高验证效率，是本文的研究核心。本文对 RFID 卡 功能和协议进行了讨论，并分解出测试点。根据 UVM 思想，规划 RFID 卡的验证 平台，并对各组件的功能实现方法进行了研究。序列库和用例库的建立，驱动器 和监视器的功能实现，参考模型算法思路，输出数据比较方法是论文的研究重点。 在仿真中，对监视器重要信号波形以及重要用例波形进行了分析。根据覆盖率报 告，功能覆盖率达到 100%，代码覆盖率均在 95%以上，已满足项目要求。本验证 环境使用较少的用例，较短的时间，完成验证任务。 关键词：验证 SystemVerilog UVM RFID 卡   Abstract With the increase of the scale and complexity of integrated circuits, the verification workload is growing exponentially. Functional verification as an important part to ensure the functional correctness of integrated circuits, faces the significant challenge and needs new verification technologies to improve the verification ability. The UVM verification methodology based on SystemVerilog language can improve the verification efficiency. The verification features of SystemVerilog language can raise the level of abstraction and reusability of verification platform and meet the requirements of verification for language functions. The verification platform architecture based on UVM and the classification, structure, function of main component UVCs are studied in this paper. Meanwhile, the inheritance relationships among base classes in the UVM standard class library are analyzed. The UVM methodology which uses SystemVerilog language to build the standard class library, gives full play to the verification ability of this language. The verified object of this paper is an RFID contactless card and the core of this paper is how to use the way of UVM to build the system-level verification environment of the RFID card and improve the verification efficiency. The function of the RFID card and the protocol are discussed, and the test points are sepa