DES算法使用vhdl硬件语言实现.docVIP

实用标准文案 精彩文档 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package des_lib is component des port (clk :in std_logic; reset :in std_logic; encrypt :in std_logic; key_in :in std_logic_vector (55 downto 0); din :in std_logic_vector (63 downto 0); din_valid :in std_logic; busy :buffer std_logic; dout :out std_logic_vector (63 downto 0); dout_valid :out std_logic ); end component; component des_round port (clk :in std_logic;