寄存器与加减乘除程序.docVIP

PAGE \* MERGEFORMAT 5 1、8位寄存器代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG IS PORT(clk , RST : IN STD_LOGIC; D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY REG; ARCHITECTURE rt1 OF REG IS BEGIN PROCESS(D,clk,RST) BEGIN IF RST=1 THEN Q ELSIF(clk=1 AND clkEVENT) THEN Q=D; END IF; END PROCESS ; END ARCHITECTURE rt1; 仿真波形图如下，请把CLK周期改成自己的学号后仿真。 2．寄存器组代码 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity REG4X8 is Port ( G,CLK : in std_logic; S : in INTEGER RANGE 0 TO 3; X : in std_logic_vector(7 downto 0); Y : OUT std_logic_vector(7 downto 0) ); end REG4X8; architecture Behavioral of REG4X8 is type xIN is array(0 to 3) of std_logic_vector(7 downto 0); signal qxIN : xIN :=((others =); begin process(Clk,G,S,QXIN) begin IF G=0 THEN Y = qxIN(S); ELSif(rising_edge(clk))then qxIN(S)=X; end if; end process; end Behavioral; 仿真波形图如下，请把CLK周期改成自己的学号后仿真。 3.加减法电路程序 超前进位模块 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CQJW IS PORT(G1,G2,G3,G4,P1,P2,P3,P4,cin: IN STD_LOGIC; C1,C2,C3,C4:OUT STD_LOGIC); END ENTITY CQJW; ARCHITECTURE rt1 OF CQJW IS BEGIN C1= (P1 AND CIN ) OR G1; C2= (p2 and p1 and cin) or (P2 AND G1) OR G2; C3= (P3 AND p2 and p1 and cin) or (P3 AND P2 AND G1) OR (P3 AND G2) OR G3; C4= (P4 AND P3 AND p2 and p1 and cin) or (P4 AND P3 AND P2 AND G1) OR (P4 AND P3 AND G2) OR (P4 AND G3) OR G4; END ARCHITECTURE rt1; （2）GP模块 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY GP IS PORT(A,B: IN STD_LOGIC; G,P:OUT STD_LOGIC); END ENTITY GP; ARCHITECTURE rt1 OF GP IS BEGIN G=A AND B; P= A XOR B ; END ARCHITECTURE rt1; （3）一位加法器模块 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADD IS PORT(A,B,C: IN STD_LOGIC; F:OUT STD_LOGIC); END ENTITY