超大规模集成电路2017秋段成华老师第四次作业.docVIP

范文 范例 参考 word版整理 Shown below are buffer-chain designs. (1) Calculate the minimum delay of a chain of inverters for the overall effective fan-out of 64/1. (2) Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, design a circuit simulation scheme to verify them with their correspondent parameters of N, f, and tp. γ=1 F=64∴f= 所以最佳反相器数目约为3 通过仿真可以得到tphl=1.3568E-11 tplh=1.7498E-11 tp0=1.5533E-11 (2)N=1时，tphl= 5.2735E-10 tplh= 8.1605E-10 tpd= 6.7170E-10 N=2时，tplh=2.2478E-10 tphl=2.5567E-10 tpd=2.4023E-10 N=3时，tphl=2.0574E-10 tplh=2.1781E-10 tpd=2.1178E-10 N=4时，tplh=2.1579E-10 tphl=2.2189E-10 tpd=2.1884E-10 从仿真结果可以看出N=3或者N=4时延迟时间最优，且N=2、3、4得到的仿真延迟时间与理论推导的时间比较接近，比例基本上是18、15、15.3，而N=1时仿真得到的延迟时间远小于理论推导的时间，但是最优结果依旧是N=3,f=4,tp=15。 * SPICE INPUT FILE: Bsim3demo1.sp--a chain of inverters .param Supply=1.8 .lib C:\synopsys\Hspice_A-2007.09\tsmc018\mm018.l TT .option captab .option list node post measout .tran 10p 6000p ************************************************************ .param tdval=10p .meas tran tplh trig v(in) val=0.9 td=tdval rise=2 +targ v(out) val=0.9 rise=2 .meas tran tphl trig v(in) val=0.9 td=tdval fall=2 +targ v(out) val=0.9 fall=2 .meas tpd param=(tphl+tplh)/2 *macro definitions ************************************************************ * *nmos1 * .subckt nmos1 n1 n2 n3 mn n1 n2 n3 Gnd nch l=0.2u w=0.4u ad=0.2p^2 pd=0.4u as=0.2p^2 ps=0.4u .ends nmos1 * *pmos1 * .subckt pmos1 p1 p2 p3 mp p1 p2 p3 Vcc pch l=0.2u w=0.8u ad=0.4p^2 pd=0.8u as=0.4p^2 ps=0.8u .ends pmos1 * .subckt inv1 in out xmn out in Gnd nmos1 xmp out in Vcc pmos1 vcc Vcc Gnd Supply .ends inv1 * *nmos2 * .subckt nmos2 n1 n2 n3 mn n1 n2 n3 Gnd nch l=0.2u w=1.12u ad=0.56p^2 pd=1.12u as=0.56p^2 ps=1.12u .ends nmos2 * *pmos2 * .subckt pmos2 p1 p2 p3 mp p1 p2 p3 Vcc pch l=0.2u w=2.24u ad=1.12p^2 pd=2.24u as=1.12p^2 ps=2.24u .ends pmos2 * .subckt inv2 in out xmn out in Gnd nmos2 xmp out in Vcc pmos2 vcc Vcc Gnd Supply .ends inv2 * *n