低功耗浮点FFT处理器设计.PDFVIP

第 16 卷 第 2 期 太赫兹科学与电子信息学报 Vo1．16，No．2 2018 年 4 月 Journal of Terahertz Science and Electronic Information Technol ogy Apr．，2018 文章编号：2095-4980(2018)02-0352-05 低功耗浮点 FFT 处理器的设计 杨琳琳，王新胜，王 静* ( 哈尔滨工业大学 信息与电气工程学院，山东 威海 264209) 摘 要 ：介绍了一种基于现场可编程门阵列(FPGA) 的低功耗可配置浮点快速傅里叶变换(FFT) 处理器的设计，可进行 4 点、16 点、64 点以及 256 点运算。采用按频率抽取的基–4 算法和基于存 储器的单蝶形结构。对蝶形运算单元进行优化，减少乘法器的数目，降低了功耗。存储单元采用 乒乓存储结构，提高了数据的吞吐率。同时，采用浮点运算提高了处理器的运算精确度。该处理 器采用中芯国际(SMIC)0.18 μm 工艺库进行综合，功耗为 0.82 mW/MHz ，并在 ACX1329-CSG324 FPGA 上实现。 关键词 ：FFT 处理器；浮点运算；低功耗 中图分类号 ：TN911.72 文献标志码 ：A doi ：10.11805/TKYDA201802.0352 Design of a low power floating point FFT processor YANG Linlin，WANG Xinsheng，WANG Jing* (School of Information and Electrical Engineering，Harbin Institute of Technology，Weihai Shandong 264209，China) Abstract：A low power，configurable and floating-point Fast Fourier Transform(FFT) processor based on Field Programmable Gate Array(FPGA) is introduced. It can operate at 4,16,64 and 256 points. Radix-4 algorithm based on frequency extraction and single butterfly structures based on memory are utilized. Butterfly operation unit is optimized by reducing the number of multipliers，and the power consumption is reduced. The memory adopts the ping-pong storage structure, which improves the data throughput rate. The use of floating-point operations improves the computing accuracy of the processor. The design of processor is synthesized by using Semiconductor Manufacturing International Corporation(SMIC)0.18 μm process library，and its power consumption is 0.62 mW/MHz. It is imp