基于cmos工艺标准单元库的扩展与优化-电路与系统专业论文.docxVIP

Abstract Title: The expansion and optimization based on standard cell library of CMOS process Major: Circuit and system Name: Yixiang Zhang Supervisor:prof .Ningmei Yu  Signature:约1飞阶叫 Si川A呻烛 lll l l l Abstract Standard cell libraries plays a very important role in various stages in the entire ASIC back-end design ，a good performance standard celllibraries can provide a strong protection for the success of the ultimate design. How to effectively explore the potential of the cell library and improve its perf01mance is one content worthy of further study. The structure of this article is divided into three pa叫s: Firstly ，we proposed the pu叩ose of this study according to the background and status of the research ，then introduced the generaJ process of ASIC backend design and the brief description of the contcnts of the standard celllibraries ，including standard cell types and some of the important process documents. Secondly from the point of view of timing ，we extended the original standard celllibrary by parallel stitching ，then compared the original cell library and the extended cell library through a concrete design example ，the conclusion suggested that the average path delay of extended cell library is reduced. In the Jast part ，by adjusting the channel size of the MOS transistors ，we optimized the original standard cells from the perspective of sub-threshold ，and analyzed the power consumption and delay overall by a concrete logic circuit example ，the conclusion indicates the energy delay product of sub-threshold celllibrary is reduced mostly and it is fit for sub-threshold surrounding. Key words: Standard celllibrary 、backend -design 、timing analyzing 、sub-threshold 、energy delay product 目录 目录 摘 要I Abstract III HYPERLINK \l _bookmark0 1. 绪论 1 HYPERLINK \l _bookmark1 1.1 研究背景 1 HYPERLINK \l _bookmark2 1.1.1 集成电路设计的发展历程 1 HYPERLINK \l _bookmark3 1.1.2 集成电路按设计方法分类 2 HYPERLINK \l _bookmark4 1.1.3 标准单元库的重要性 3 HYPERLINK \l _bookmark5 1.2 研究现状 3 HY