基于FPGA数字频率计的设计..docVIP

河北大学2013届本科生学年论文（课程设计） 装订线 装 订 线 本科生学年论文（课程设计） 题目：基于FPGA数字频率计的设计 学 院 学科门类 专 业 学 号 姓 名 指导教师 2012年10月20日 基于FPGA数字频率计的设计 摘 要 频率计基于电子设计技术，实现了在一片现场可编程门阵列上的数字频率计的设计，也是计算机、通讯设备、音频视频等科研生产领域可缺少的测量仪器。本文主要介绍一种以FPGA为核心，基于硬件描述语言VHDL的数字频率计设计与实现,并在EDA(电子设计自动化)工具的帮助下，用大规模可编程逻辑器件(FPGA/CPLD)实现数字频率计的设计原理及相关程序。特点是：无论底层还是顶层文件均用VHDL语言编写，避免了用电路图形式设计时所引起的毛刺现象；改变了以往数字电路小规模多器件组合的设计方法，整个频率计设计在一块FPGA/CPLD芯片上，与用其他方法做成的频率计相比，体积更小，性能更可靠。本论文主要讲述了使用FPGA实现的数字频率计，它采用VHDL语言编程，用Max plus = 2 \* ROMAN II集成开发环境进行波形仿真，编译，并下载到FPGA中。正是因为数字频率计的应用是如此的广泛，才使得它的作用是如此的重要，所以更应该去关注和研究[1]。 关键词：FPGA；频率计；集成电路；电子设计自动化 The Design of Digital Frequency Meter based on the FPGA ABSTRACT Digital frequency meter based on EDA technique is presented, which is realized in FPGA，it is the indispensable measure instrument of the computer, communication equipment, audio video ,the scientific research and production field .This paper mainly introduces a kind of digital frequency meter ,which core strategy is Field Programmable Gate Array and is based on VHDL .At the help of EDA ,it realizes the goal of Design Principle and relative program by FPGA or CPLD .Its characteristic is that no matter the underlying file nor top-level file are written by the VHDL language .This process can avoid the phenomenon caused by circuit diagram forms designation .It also change the design method of previous digital circuit .The whole frequency meter is designed in a piece of FPGA or CPLD chip .Compared with other methods of making the frequency meter ,it is smaller and more reliable .This paper is focuses on the use of FPGA to achieve the digital frequency meter ,It use VHDL language programming ,uses the simulation waveform Max plus II integrated development environment compiler, and downloaded to the FPGA。Because of the function of digital frequency meter is so important ,its application is so widely and we should to pay attention to and research. Key words :FPGA；Digital frequency meter；IC；EDA 目　　录 1　绪论··········