《抗软失效的新型时序电路单元设计论文》-毕业论文设计（可用）.docxVIP

本科生毕业论文 题目：抗软失效的新型时序电路单元设计 Novel Soft Error Robust Latches and Flip-flops 姓 名： 学 号： 1000012825 院 系： 信息科学技术学院 专 业： 微电子系 导师姓名： 二〇一四 年 五 月 北京大学信息科学技术学院学士论文王子一 PAGE \* MERGEFORMAT15 摘要 随着半导体工艺的进步，器件的特征尺寸逐渐减小。在深亚微米和纳米技术时代，电路的可靠性正逐步成为电路设计者和研究人员主要关注的问题。工艺尺寸的减少导致集成电路对宇宙射线和放射性元素产生的粒子更加敏感。当电路中的敏感节点受到粒子撞击时，可能会产生瞬时电压电流的变化。这种非永久性电路状态的破坏，称为软失效（Soft Error）。 当粒子撞击时序电路中的存储单元时，会导致存储状态发生翻转，并逐级传递下去，影响时序逻辑电路正常功能的实现。设计较低软失效率的时序电路单元对集成电路的发展具有重要意义。 本文分析了软失效的产生原理，并研究了目前主流的几种不同抗软失效电路的作用机制。针对应用广泛的Quatro-8T抗软失效电路中存在的翻转问题进行了改进，进一步提高了电路的可靠性，使得电路的抗软失效能力得到加强。同时，基于40nm工艺，对改进后电路单元构成的锁存器和触发器进行了仿真，实现正确的时序逻辑功能。 关键词：软失效，抗软失效电路，Quatro-8T电路单元，触发器，电路可靠性 Abstract As we enter the era of nanotechnology, reliability issues of circuits become one of the major concerns for circuit designers and researchers. With continuous scaling of CMOS technology, the circuits are becoming more and more vulnerable to radiation and cosmic rays. When a particle strikes a sensitive node in circuit, a transient fault may appear as an electrical pulse. This non-permanent fault is called soft error. When a particle strikes a node inside a latch or flip-flop, the stored value of the latch may be flipped based on the amount of deposited charge by the particle. As a result, the fault would propagate through the combinational path and be captured by the next sequential circuit as a faulty value. Hence, the design of soft error robust circuit has become significant to the development of integrated circuits. This paper analyzes the theory of soft error, and studies different soft error robust circuits. A novel circuit based on Quatro-8T is proposed to improve the reliability and decrease soft error rate. HSPICE simulation results based on 40-nm technology reveal that the novel latch and flip-flop work correctly. Key words: soft error, soft error robust circuit, Quatro-8T cell, flip-flops, circuit reliability 绪论 随着科学技术的日益进步，半导体工艺的特征尺寸在逐渐减小。于此同时，大规模集成电路也在许多高科技领