数字设计课件第9章存储器、cpld和fpga.pptVIP

Chapter 9 Memory、CPLD and FPGA 本章只要求存储器中的ROM及其用于组合逻辑电路的设计 memory 9.1 Read-Only Memory (ROM) 1. basic strcture 2. Internal ROM structure 3. Two-dimensional decoding MOS transistors as storage elements 4. commercial ROM types mask-programmable ROM , array connections are programmed during semiconductor manufacture using a mask. very fast. very dense. expensive, 2-4 week turn-around, low power Programmable ROM(PROM), fuses to program once in the field, use PROM programmer, inexpensive EPROM（Erasable PROM）, fuses implemented using floating-gate MOS transistors to program 10k~100k times in the field, erased by flooding with UV light. E2PROM（Electrically EPROM）, byte-program, individual stored bits may be erased electrically. flash E2PROM, a specific type of E2PROM that is erased and programmed in large blocks floating-gate MOS storage elements 按照数据的输入/输出分为串行EEPROM和并行EEPROM。 串行EEPROM：在读写数据时，输入/输出时通过2线、3线、4线或SPI总线等接口方式进行的。 并行EEPROM：数据的输入/输出是通过并行总线进行的。 近期，低功耗，写入/擦除速度快的产品很多，如Microchip公司的新型8千位、16千位串行EEPROM，最快时钟10MHZ，写入时间5ms，电流3mA,内置写保护功能，可保存数据达200年，承受100万次擦写。Atmel公司的AT24C××系列…… 5. Using ROM for “random” combinational logic functions Store the output value of a given truth table in the ROM, the function inputs are connected to the address input . Exp1: the dual polarity decoder.(P.801) Exp2: 4×4 multiplier More Exp.: ROM在同步时序电路设计中的应用 位序列信号的产生：计数器 — ROM法 设计一个码长为8位的序列信号发生器，信号序列 ROM在组合电路设计中的应用 试用8×4ROM实现如下组合逻辑函数 F1=AB+A’C, F2=AB+B’C 解：先化作标准和式 以输入变量作为ROM的地址，将输出值放入ROM单元。 用16字×4位ROM实现2输入变量的与非、或非、异或和同或 实现4位二进制码—格雷码的转换 Random-access memory (RAM) 9.3 Static Random-Access Memory 2n×b RAM structure SRAM internal structure A static-RAM cell SEL_L、WR_L both negated, D latch hold the data； SEL_L is asserted, tri-state buffer enable, data output (read); SEL_L、WR_L both be asserted, D latch open, a new bit is stored. synchronous SRAM A bit of storage is also a latch. Control, addresses and writing or reading data are all occurred at the edge of the sa